`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2022/03/16 16:43:50
// Design Name: 
// Module Name: ALU
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////
import Params::*;
`include "Parameters.v"
module ALU(
input logic [31:0] Operand1,
input logic [31:0] Operand2,
input AluOp AluControl,
output logic [31:0] AluOut
    );

always_comb
begin
    case(AluControl)
       SLL:AluOut=Operand1<<(Operand2[4:0]);               //逻辑左移
       SRL:AluOut=Operand1>>(Operand2[4:0]);               //逻辑右移
       SRA:AluOut=$signed(Operand1)>>>(Operand2[4:0]);              //算术右移
       ADD:AluOut=Operand1+Operand2;                       //加
       SUB:AluOut=Operand1-Operand2;                       //减
       XOR:AluOut=Operand1^Operand2;                       //异或
       OR:AluOut=Operand1|Operand2;                         //或
       AND:AluOut=Operand1&Operand2;                        //与
       SLT:AluOut=($signed(Operand1)<$signed(Operand2))?32'd1:32'd0;            //小于置位
       SLTU:AluOut=(Operand1<Operand2)?32'd1:32'd0;                             //无符号小于置位
       LUI:AluOut=Operand2;                                                     //LUI指令
       default:AluOut=0;
    endcase
end
endmodule
//ALUContrl
/*
    `define SLL  4'd0
    `define SRL  4'd1
    `define SRA  4'd2
    `define ADD  4'd3
    `define SUB  4'd4
    `define XOR  4'd5
    `define OR  4'd6
    `define AND  4'd7
    `define SLT  4'd8
    `define SLTU  4'd9
    `define LUI  4'd10
*/
